1. Field of the Invention
The present invention relates to sequence control, and more particularly to a central processor suitable for use in sequence control.
In general, from the viewpoint of the controlled content, D.D.C. (Direct Digital Control) is divided broadly into numerical operation control dealing with numerical data and sequence control performing logical operation of 1-bit data. 1-bit data corresponds to, for example, an ON/OFF signal generated from a relay contact.
The present invention relates to a central processor in a computer system, and more particularly to a central processor optimized for use as a P.C. (Programable Controller) which is to be employed in D.D.C. for general industries.
With increase in the number of contact information from the plant to be controlled, there has been an attempt to provide a system in which such information is processed using a digital computer. In not a few cases, however, processing of information providing an indication with 1-bit is rather inefficient for computers adapted to execute processing for on a word basis.
The present invention has been accomplished with a view of solving the problem as mentioned above and it is intended to provide a processor which can improve the processing ability through parallel execution of bit processing using a single unit of a central processor.
2. Description of the Prior Art
Because a general purpose digital computer is adapted to run processing in words, the logical sum of a first bit and a second bit in the same word, for example, is calculated as follows.
Namely, it is necessary that the data word to be processed is once stored in a register, then the data word is shifted to put the second bit in the position of the first bit, and then the new content at that position is added to the content previously stored in the register to obtain the logical sum.
There is also known a system so configured that each bit is given an address and an arithmetic operation is run by a one-bit accumulator (e.g., Motorola Co., Model MC14500B). However, this system has a limitation in its processing speed as a matter of course, because the data capable of being processed simultaneously is only 1 bit. Further, it is required to prepare a stack memory or a working memory for the so-called parenthesis operation (e.g., output O1 is given by AND between OR of inputs I1, I2 and OR of inputs I3, I4: O11=(I1+I2).multidot.(I3+I4)) which occur frequently in sequence control, thus resulting in a fear that processing becomes complicated and the processing speed is lowered. In addition, Japanese Patent Application Laid-Open Official Gazette Nos. 55-116141 and 54-124646, disclose a method using specific processors corresponding to the respective bits.
Furthermore, examples of a sequence controller based on processing of a data word are described, for example, in U.S., Pat. Nos. 4,316,260 and 3,944,987.